Test apparatus for determining continuity paths on a multiterminal arrangement

ABSTRACT

Test apparatus preferably comprising a signal forming means connected to a selected drive point which is one of the terminals, scanning apparatus for scanning the plurality of terminals, means for ascertaining electrical continuity between the driven point and each scanned point whereby continuity is either desired or undesired depending on the accuracy and faithfulness of wiring to the plurality of terminals, and output means identifying errors in test point wiring between the terminals.

United States Patent Yarbrough May 23, 1972 54] TEST APPARATUS FORDETERMINING 3,219,927 11/1965 Topp et al ..324/73 CON'HN UITY PATHS AMULTI- 3:333??? H38 3"? 553 21 2 TERMINAL ARRANGEMENT 3,476,888 11/1969Rollms et al. ....324/66 X [72] Inventor: Kenneth A. Yarbmugh, 1030Medalist, 3,311,890 3/1967 Waaben ..324/73 UX Dallas 75232 PrimaryExaminerGerard R. Strecker [22] Filed: Mar. 2, 1970 Attorney-Donald Gunn[21] App]. No.: 14,796 57 ABSTRACT Related US. Application Data Testapparatus preferably comprising a signal forming means connected to aselected drive point which is one of the ter- [63] Continuatlon of Ser.No. 622,698, Aug. 23, 1967, minals scanning apparatus for scanning heplurality of ten minals, means for ascertaining electrical continuitybetween the driven point and each scanned point whereby continuity isU.S. either desired or undesired depending on the accuracy and [51] Int.Cl ..G0ll' 31/02 faithfulness of wiring to the plurality of terminals,and output [58] Field of Search 324/51, 66, 73 means identifying errorsin test point wiring between the terminals. [56] References Cited 9Chins, 7 Drawing Figures UNITED STATES PATENTS 3,441,849 4/1969 Bennettet a1 ..324/73 TAPE READER x DR\VE RamsTER Ilsa DECQDE DRlVER ColN -HlDETEcTOR l'ra Y DRtv z REGISTER Y'suw REGl$TER ecooe DRIVER DEQODEDHDJER ERROR DETECT APE srep COMMHN DR\VER PAR|$ON REGISTER QOlNCI DENCEDETEQTOR x some REGISTER Patented May 23, 1972 X D\\IE REGISTER ($D\ 5Sheets-Sheet 2 204 x omva RECnsTER (sow J l I 22-4 DECODE Dram/ER I r"(I ,5 72 ul Z I" KL 70 m a 0 Lalo U u: o

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TEST APPARATUS FOR DETERMINING CONTINUITY PATHS ON A MULTI-TERMINALARRANGEMENT This application is a continuation of application, Ser. No.622,698, filed Aug. 23, 1967, now abandoned.

SUMMARY OF PROBLEM AND INVENTION Numerous multiple terminal matrixarrays fabricated for use in electronic assemblies are wired fromtemiinal to terminal. The permutations and combinations of wiringintroduce the likelihood of error and therefore the necessity for veryaccurate testing. Consider, for purposes of discussion, a multipleterminal pattern having one hundred terminals in each column and row.The total number of terminals is 10,000 terminals. Quite often, thewiring pattern for a large grid will vary in the manufacture oftelephone equipment, computers, electronic test equipment, interfacingapparatus, and the like. Given ten thousand points, it is quitedifficult to verify or confirm both the presence of desired wiringpatterns in the matrix and the absence of undesired wiring connections.Of course, if only one or two wires are joined to the multipleterminals, it is easy to visually inspect the apparatus. However, toverify accurate assembly of the terminalsand wiring harness with anumber of wires extending over the terminal board is difiicult, if notimpossible, with any degree of reliability.

Often a basic terminal board is devised wherein differing models ofequipment are fabricated by use of differing wiring patterns on thebasic terminal pattern. For instance, in a particular product line, alarge multiple point terminal board basic to all models is used foroptional wiring patterns connecting several of the thousands of points.It is with a view of testing multiple terminal apparatus that thepresent apparatus provides high-speed testing of the wiring betweenterminals, verification of all desired wiring paths, and proof thatundesired wiring paths are absent. Therefore, the present invention issummarized as providing an input means for receiving from a data mediumthe coordinates descriptive of points in a wiring pattern, means forimposing on a selected terminal a predetermined electrical conditionwhereby any terminal wired thereto will indicate continuity, means forscanning a plurality of terminals to ascertain connection of any of theterminals to the driven terminal, and means operative with terminalscanning to determine the presence or absence of an error in the wiring.

One object of the present invention is to provide a new and improvedtest apparatus for a plurality of terminals which scan at electronicspeeds all of the plurality of points with respect to one selected pointto ascertain desired patterns of continuity.

Another object of the present invention is to provide a new and improvedtest apparatus for a plurality of terminals whereby the terminals arescanned sequentially in a two-coordinate system.

An important object of the present invention is to provide a new andimproved high-speed continuity test set wherein data is input indicatinga first or driven point and all points having continuity therewith areascertained.

Yet another object of the present invention is to provide a new andimproved high-speed continuity test set wherein a first point isselected and the remaining terminals are scanned and a second test pointis selected wherein the scanning for continuity with the second pointavoids redundant scanning of points tested earlier in the test routine.

7 Yet another object of the present invention is to provide a new andimproved high-speed continuity test set for use with a plurality ofterminals whereby desired paths of continuity are confirmed while theapparatus tests for continuity at additional although undesiredterminals.

A elated object of the present invention is to provide a new andimproved high-speed continuity test set which ascertains and prints outthe information identifying terminals having undesired continuity withother terminals in the pattern.

Yet another object of the present invention is to provide a high-speedcontinuity test set for comparing experienced wiring patterns withintended wiring patterns among a plurality of terminals which includesmeans indicating the nature of errors and their location.

Other objects and advantages of the present invention will become morereadily apparent from a consideration of the included drawings wherein:

FIG. 1 is a block diagram schematic of the high-speed continuity testset of the present invention;

FIG. 2 is a simplified representation of a terminal pattern introducingthe philosophy of the test of the present apparatus;

FIG. 3 is a partial schematic of circuitry for grounding a selectedterminal to initiate testing for continuity with other terminals in theplurality of terminals;

FIG. 4 is a schematic of scanning apparatus for testing the plurality oftenninals for continuity with the terminal grounded by the circuitryshown in FIG. 3;

FIG. 5 is a programming model of the plurality of terminals,

Table l is the encoded test data for the wiring shown in the programmingmodel of FIG. 5;

FIG. 6 is a more detailed schematic of a BCD decode driver circuitry;and,

FIG. 7 is a detailed schematic of a BCD decode comparator.

Attention is first directed to FIG. 1 of the drawings which illustratesin detail a block diagram schematic of the high speed continuity testset of the present invention which is indicated by the numeral 10. Thetest set is adapted to test a plurality of terminals which are indicatedby the numeral 12. Note should be taken of the wide range of variationspermitted in the terminals 12. They are preferably described by acoordinate system for the rows and columns; a matrix including rows and100 columns provides 10,000 terminals in one example described herein.Of course, the actual physical relationship of the terminals, one to theother, is of no consequence to the present invention. For instance,several terminals of the plurality of terminals may be physically remotefrom the remainder. This is of no consequence to use of the presentinvention. Moreover, the identification pattern of terminals isrectangular or square, as desired. In any event, the apparatus of thepresent invention is devised to cooperate with a plurality of terminalsdescribed by a two-coordinate system, with the maximum value of eachcoordinate being 100 in the chosen example.

For better understanding, three points in the matrix are presentlydefined. A drive point is first selected and a continuity condition isimposed on the drive point. For the present disclosure, the drive pointis grounded, although, of course, other voltage levels can be imposed onthe drive terminal. Secondly, a comparison point is the terminal of theplurality of terminals at which continuity with the drive point isexpected. There may be only one, or more than one, comparison point fora given drive point, dependent on the wiring pattern. Thirdly, the scanpoint is the point being tested by the apparatus 10 at any giveninstant, and it may or may not be a comparison point. In operation, adrive point is first defined by coordinates and then one comparisonpoint is defined for cooperation with the stated drive point. Aftercycling or scanning through the plurality of points to the comparisonpoint, the apparatus then receives the coordinates of additionalcomparison points for the first drive point, if any. In the alternative,a new drive point is defined and grounded after which time a comparisonpoint is ascertained and the testing begins anew. With these definitionsin view, attention is redirected to FIG. 1 of the drawings whichincludes a tape reader 15 through which data is input to the presentinvention as will be described.

The tape reader 15 is one means of inputting data to the high speedcontinuity test set 10. The data input through the tape reader 15includes the following: the coordinates of both the drive point to beselected for the apparatus and the comparison point. Each of the twopoints is described by two coordinates, preferably labeled X and Y"coordinates hereinafter. Since the coordinates can range from zero to 99(a span of 100 units), unit and decade decimal number representation isincluded in the medium read by the input device 15. These two points aredefined by a total of eight decimal numbers, four of the decimal numbersidentifying the drive point and the remaining four identifying thecomparison point. The data for the drive point and the data for thecomparison point is separated, one from the other, by its location onthe tape. Thus, selected columns in the tape are reserved for the drivepoint and selected columns in the tape are reserved for the comparisonpoint. In actual configuration, the above apparatus may take the form ofa tape which is perhaps 32 columns in width to provide the BCDrepresentation of the eight decimal numerals. 1n the alternative, ablock tape reader is used with selected locations in eachv data blockbeing designated for either drive point data or comparison point data.Even another alternative is the serial arrangement of the data on anarrow width tape, it being recognized that there are usually eightperferations across the tape, wherein four perferations transfer the BCDnumber while the remaining four perferations designate the storageregister for the BCD number. At any event, the means 15 is an inputdevice for receiving data from a storage medium.

Hand operated input devices such as thumb wheels, switches or the like,can be used to set in the data in lieu of the tape reader means 15.However, this alternative is best suited for short runs of the apparatus10.

Preferably, the input data is in the form of binary coded digits. Eachdecimal digit is represented by four bits of data. The encoded decimaldigits are communicated to components to be described by a number ofinput conductors 16 through 19, inclusive. Each of the conductors shownin FIG. 1 is in reality four conductors which are shown as one forclarity. Each of the four conductors carries the bits weighted to havevalues of l, 2, 4 and 8.

Attention is directed to input conductors 16 and 17 which provide thedrive point selection information. The conductors 16a and 17acommunicate with the X and Y" drive registers indicated by the numerals20 and 21. The conductors being more specifically indicated by thenumerals 16a and 17a. The registers 20 and 21 are capable of acceptingnumbers between zero and 99 to provide the 100 values of each of the twocoordinates describing the plurality of terminals 12 in the exemplarystructure considered herein. Each of the registers 20 and 21 isconnected to a decode driver 22 and 23 which cooperate to ground theselected drive point identified by the data input by the means 15. Theoperation of the drivers 22 and 23 will be described hereinafter.

The data from the tape reader 15 is input through conductors 16b and 17bto scan registers 24 and 25. Scan registers 24 and 25 cooperate withdecode drivers 26 and 27 which are similar in function to the drivers 22and 23.

A contrast should be noted between the data placed in registers 20 and21 as opposed to the data stored in registers 24 and 25. The data placedin the drive registers 20 and 21 is essentially static since itindicates the drive point. The data in the registers 24 and 25 isdynamic since it indicates the coordinates or location of the particularterminal scanned at any one instant, recognizing that the scanning rateis perhaps 100,000 or more terminals per second. More will be notedconcerning these differences hereinafter.

The input conductors l8 and 19 from the tape reader means 15 communicatewith a pair of comparison registers 28 and 29. Coincidence detectors 30and 31 obtain comparisons between the scan and comparison registers foreach of the two coordinates. As previously noted, the comparison pointis the next terminal anticipated to have continuity with the selecteddrive terminal. Again, it should be recalled that several terminals maypossibly have continuity with one drive point, and in this event, therewill be several comparison points for one drive point. The coincidencedetectors 94 comparators 30 and 31 determine equality of the coordinatesstored in the various registers to determine when the scanned terminalis the same as the comparison point. This is of significance because theterminal is expected to have continuity with the drive point.

Additional means to be described test for continuity to confirm theanticipation indicated by the coordinates stored in the registers 28 and29.

When a comparison is obtained from the detectors 30 and 31, the outputsthereof are communicated to an AND gate-32 which communicates at itsoutput with an exclusive OR gate 34. The OR gate 34 provides a scaninhibit signal to a scan clock means 36. The scan clock means 36provides timed pulses through a conductor 37 to the scan register 24.During scanning of the plurality of terminals 12, the information in theregister 24, having been first set by the data word input over theconductor 16b, is incremented by the pulses supplied over the conductor37. When the scan register 24 overflows by counting to the highestpossible value to be stored therein, the overflow creates a pulse in aconductor 38 to the scan register 25. It should be understood thatoverflow or spill-over is in the form of an increment added in theregister 25 to increase the count stored in the register 25. Moreover,this only occurs simultaneous with resetting of the register 24 to zero.It will be appreciated that, with the above over-flow sequence, rows ofthe terminals 12 are scanned sequentially. For instance, the row 12a isscanned from left to right as shown in the drawing, then the row 12b isscanned. The sequence is repeated until the row 12c is scanned, and uponarrival at the last terminal, the scanning is completed for the givendrive point and the tape reader means 15 is advanced to the next drivepoint. It will be appreciated that the interlacing of test points, rowupon row, is controlled by inputting the high frequency pulses from thescan clock 36 to the scan register 24, and thereafter incrementing thescan register 25. Of course, the above described technique can beapplied to columns with the scanning accomplished vertically in thevarious columns of the matrix 12.

Attention is next directed to the OR gate 40 which provides an outputlevel of a conductor 41 when the scanned terminal has continuity withthe driven terminal. The OR gate 40 passes a pulse from the scannedterminal (selected by the scan registers 24 and 25 and the decodedrivers) which indicates that continuity has been ascertained.

The conductor 41 is communicated to the exclusive OR gate 33. Aspreviously noted, the gate 32 provides a signal for an anticipatedcontinuity. Should the fact of continuity be established for anyterminal and a signal formed by the gate 40, the conductor 41 inputs thesignal to the gate 33 coincident with the signal from the gate 32. Theexclusive OR gate provides no output if signals arrive at both inputs.This is, of course, an indication of no error. On the other hand, theabsence of either input signal forms an error signal on the conductor 42which communicates with a digital printer 43. Other inputs to thedigital printer 43 are the numbers stored in the registers 20, 21, 24and 25 wherein the registers are wired to the printer 43 which isenabled to print the data in the registers on occurrance of an error.The error print-out includes the coordinates of the drive and scanterminals. Moreover, the conductor 42 is an input to the OR gate 34which also inhibits operation of the scan clock 36 for an interval topermit the digital printer 43 to process the information, it beingappreciated that the digital printer 43 is slower in operation than theelectronic apparatus described hereinabove.

It is necessary to ascertain the nature of the error identified by thecoordinates printed by the digital printer 43. To this end, anerror-phase detection circuit 46 is provided. The OR gate 40communicates through the conductor 41 to the error phase detectioncircuit 56. Likewise, an input is obtained through a conductor 47 fromthe gate 32 which indicates coincidence between the scanned terminal andthe comparison point. The existence of continuity at a scanned terminalin excess of that desired is arbitrarily defined as a positive error andthe error phase detection circuit means 46 provides a signal on theconductor 48 to include a plus mark printed by the printer means 43. Onthe other hand, should the comparison point in the grid coincide withthe scan point (sensed by the coincidence detector means) and indicatedby the AND gate 32,

and further should the OR gate 40 provide no output indicating theabsence of continuity in actuality, a wire is missing, and a minus signis printed by the digital printer means 43. This indicates a deficiencyin the actual wiring wherein continuity is anticipated at the terminalbut the connection is not in fact made.

The conductor 38 and an additional conductor 49 from the registers 24and 25 are both input to a tape step command generator 50. As previouslydescribed, the conductor 38 provides a signal when the scan register 24over flows, or has therein the maximum number which can be stored. Thiscondition also occurs in the scan register 25. Overflow of both scanregisters at the same instant indicates that the scanning has proceededfrom the terminal represented graphically in FIG. 1 at the upper left tothe terminal at the lower right. This, of course, implies total scanningof all terminals. Again, the physical relationship and arrangement ofthe terminals is subject to wide variation. At any event, the conductors38 and 49 are input to the means 50 which indicates overflow of bothregisters 24 and 25. When overflow is simultaneous, the means 50provides an output signal on the conductor 47 which serves as the tapestep command for the tape reader means 15.

It should be noted that the tape reader means is stepped by occurrenceof several events. For instance, should the scanning of the plurality ofterminals 12 arrive at a comparison point as sensed by the coincidentdetectors 30 and 31, the AND gate forms a signal on the conductor 47which advances the tape. Secondly, should scanning proceed to the lastterminal and the signal be formed by the tape step command means 50, thetape is also stepped to obtain new information for the presentinvention. 7

It is believed that the foregoing describes generally the overalloperation of the present invention. However, as a means of furtheringunderstanding of the present apparatus, attention is directed to FIG. 2.

A simplified terminal pattern is indicated in FIG. 2 with a number ofterminals, nine to be exact, indicated by the numerals 56-1through'56-9, inclusive. It will be noted that a wiring pattern isanticipated which includes the first, fifth and eighth terminalsconnected by the conductor 57. A switch 58 connected to the terminal56-1 is closed to ground. A positive voltage, 12 volts in the preferredembodiment, is communicated with the terminal 56-1 through a resistor59. In testing the nine terminals shown in FIG. 2, a volt meter probe 60connected with a volt meter 61 is connected to each of the terminals inany desired order to ascertain continuity with the terminal 56-1. Withthe switch 58 closed to ground the terminal, all continuous points arelikewise grounded. On the other hand, all terminals not so grounded areat the positive voltage resulting from their connection with the B+supply. Hand techniques will scan nine terminals for continuity withadequate speed. However, hand techniques are certainly unreasonable forlarge arrays including 5 or 10,000 terminals or even more. For anunderstanding of means for automatically grounding (or driving) theselected terminal 56-1, attention is next directed to FIG. 3 of thedrawings.

It will be noted first of all that the X" and Y drive registers and 21are shown in FIG. 3 communicated with the decode drivers 22 and 23. Thelogic output of each of the decode drivers is a true or one signal usedin the following manner: The decode driver forms a level on a selectedconductor numbered with the X coordinate of the drive point. Forpurposes of illustration, the second conductor 63 is energized; theconductor 63 is the base voltage for several transistors arranged in acolumn and identified by the numerals 64, 65 and 66. Of course, the Xdesignation is input by the tape reader means 15 (see FIG. 1).

The Y" select information chooses rows of transistors to be energized inthe matrix as will be described. More particularly, the decode drive 23outputs a logic level which is a one or true signal to either oftransistors 67, 68 or 69. For purposes of illustration, the selectedtransistor is the transistor 68. The signal from the decode driver 23 (alogical one) is applied to the base of the transistor 68 to turn on theswitching transistor. It will be noted that the emitter of thetransistor is grounded. When the transistor is switched on, iteffectively grounds a conductor 70 which provides the emitter connectionfor transistors 71, 65 and 72. It will be noted that base conditions onthe transistors 71 and 72 are insufficient to cause conduction of thesetransistors. However, the transistor 65 has both the proper base voltageand the needed emitter connection. As the saturatedtransistor conducts,the terminal 56-5, now indicated by the X-Y" coordinates 2,2- iselectronically grounded. It will be noted that the transistors 64 and 65have suitable base voltages to cause conduction but do not have properemitter connections to permit current flow.

The foregoing illustrates how a selected point is grounded. For purposesof clarity, the resistor 59 (see FIG. 2) and the positive supply havebeen omitted from FIG. 3; together, they complete the collector circuitfor each transistor. As a matter of nomenclature, the terminals areidentified in FIG. 3 with the X-Y coordinate system rather than serialnumbering which is preferable for large arrays best tested by thepresent invention.

In summation, it will be noted that each terminal is associated with acollector resistor communicated with a B+ supply. When driven, theterminal is electronically grounded by operation of the decode drivers22 and 23 which respond to the X and Y" coordinates of the .driventerminal. As defined herein, the driven terminal is effectively groundedby turning on a switching transistor utilizing the collector resistorand associated positive supply to complete the circuitry. Thus, when thedriven terminal is grounded, all points having continuity therewith arelikewise grounded.

Attention is next directed to FIG. 4 of the drawings which indicatesapparatus for scanning an examplary matrix also including nineterminals. Since the function of FIG. 4 is to convey an understanding ofhow the apparatus scans all terminals save the driven terminal, thefirst terminal (having the coordinates 1,1) is grounded by operation ofthe apparatus described hereinabove. Therefore, scanning the remainderof the terminals will be explained assuming the terminal having the X-Ycoordinates 2,2 is hard wired to the grounded or driven terminal locatedat 1,1. The decodedrivers 26 and 27 are similar in function andcommunicate with a number of conductors arranged either in rows orcolumns. The X scan register inputs a number to the driver 26 whichselects a numbered conductor to be grounded as required by the number inthe scan register 24. In the example of FIG. 4, the conductor 75 isgrounded whereas the remaining conductors are not. Likewise, a number inthe Y" scan register 25 is decoded by the means 27 whereby a conductor76 is also grounded whereas the remainder of conductors from the decodedriver 27 are not grounded.

By definition in the two coordinate system, only the terminal atcoordinate 2,2 obtains coincidence of scan signals. The scanned orselected terminal determined by the coordinates input to the registers24 and 25 is then tested for continuity with the driven point in thefollowing manner.

As previously noted, each of the terminals is communicated with somepositive supply through a resistor 59. If there is continuity, the hardwiring to the driven terminal grounds the scanned terminal. This pullsthe voltage at the terminal from the supply voltage to approximatelyground potential. A NOR gate 80 having three input terminals iscommunicated with the terminal in question, the X line 75, and the Y"line 76. The X and Y lines input two false signals to the NOR gate 80.Should the terminal bearing coordinates 2,2 be wired to the driventerminal and therefore grounded, the third input to the NOR gate 80 islikewise false, and the output of the NOR gate 80 is a true signalsupplied to a conductor 81. The conductor 81 communicates with themassive OR gate 40 described previously.

While the foregoing describes how the condition of one terminal isascertained, it should be generalized that each of the plurality ofterminals has its own NOR gate wired in the same manner. Moreparticularly, each NOR gate has three inputs which include a connectionto the terminal itself, a connection to the Y scan line, and aconnection to the X scan line with the X and Y scan lines specified bycoordinate numbers. Moreover, all of the NOR gates, there being one perterminal, are input to the massive OR gate 40 which has as many inputsas there are terminals. In the example shown in FIG. 4, the gate 40 hasnine inputs and will provide a true output should any of the NOR gatesprovide a true input to the gate 40.

While the foregoing describes the operation when continuity isdetermined at a given terminal, whether expected or unexpected, it willbe appreciated that the scanning means is stepped as the X scan register24 is incremented at a high rate of speed. More will be noted concerningthis hereinafter.

Attention is next directed to FIG. of the drawings which illustrates a25-terminal pattern for purposes of example. The grid pattern is shownin a 5 by 5 arrangement, bearing X? and Y coordinates. Table 1 lists thecoordinates for the various drive points and comparison points. Oneconductor 82 is wired to five terminals in one pattern. The uppermostand leftwardly located terminal is selected as the drive point since itis approached systematically first counting from the origin of thecoordinate system. Therefore, the first entry in the table ofcoordinates is the drive terminal for the conductor 82; one driveterminal per wire is needed. The next four entries included in Table lare the coordinates of anticipated points of continuity, all common tothe conductor 82. In operation, the apparatus grounds the drive pointterminal which has the coordinates 0,0. Scanning commences by rows, andruns at a high rate of speed until the terminal having the coordinates1,1 is reached. At this juncture, continuity is ascertained to confirmthe wiring. Thereafter, the coordinates of the second comparison point(1,2) are entered in the comparison register and scanning continuessequentially in the second row of the array. The scanning proceeds untilthe next comparison terminal. is reached. The above routine is repeatedsequentially until the last comparison point is ascertained, the pointbearing coordinates 3,3. After verification of this terminal, thescanning process continues through all of the remainder of terminals tothe lower right hand terminal shown in the programming model of FIG. 5.Scanning to this terminal causes spill over of the scan registers andthe tape step command means 50 (see FIG. 1) which then advances the tapeto the next drive point.

In FIG. 5, the next drive point bears the coordinates 1,0 and is thefirst of five terminals common to the conductor 83. The proceduredescribed for the conductor 82 is repeated wherein the comparison pointsare certified to be common with the drive point and all remainingterminals are confirmed to not have continuity with the conductor 83.Continuing on down Table l, conductors 84 and 85 are likewise confirmed.

Certain economies in programming the data input to the test apparatusreduce the operation time. Attention is directed to the four drivepoints listed in Table 1. It will be noted that the drive points arearranged proceeding from the upper left corner of the array toward thelower right comer. Considering the last drive point which has thecoordinates of 3,0, usually there is no benefit in scanning terminals tothe left of this drive point. This is because terminals to the left orabove have been previously tested with other drive points. The scanningfrom the last drive point through a lesser number of terminals reducestotal scan time. Implementation is achieved by connection of theconductors 16b and 17b to the scan registers as shown in FIG. 1. Ofcourse, on omission of these conductors to the scan registers, it ispermissible to start scanning from the terminal having the coordinates0,0. However, through the use of the conductors 16b and 17b input to thescan registers, as the test program is executed, the number of terminalsremaining to be scanned in the latter portions of the program issubstantially reduced.

To enhance the speed of operation a means can be included to prevent thesystem from detecting continuity of the drive point with itself.Recalling the fact that the drive point coordinates are input both tothe drive registers and to the scan registers, the first test of theterminals 12 will reveal continuity of the drive point itself. Ratherthan obtain the obvilusly anticipated continuity, it is preferably toaugment the number in the X" scan register by one prior to initiatingscanning of the terminals.

Attention is next directed to FIG. 6 of the drawings which illustrates adecode driver for use withthe present invention. As shown in FIG. 1,four decode drivers are communicated with the matrix of terminals 12. Aswas shown in FIG. 3, decode drivers 22 and 23 provide true level signalswhich, depending on the logic levels chosen, are preferably positivevoltages such as 6 or 12 volts. As shown in FIG. 4, decode drivers 26and 27 provide false logic levels which are preferable ground potential.Of course, other voltage levels can be used by choosing differentcircuit elements but it is preferable to select ground as the falselevel because of the possibility of grounding a terminal to the chassiseven with no wired connection to it. However, the differences are notedin the drive decoders and the scan decoders as being within the purviewof one skilled in the art. In FIG. 6, two portions of the X" driveregister are represented at and 91. The two portions are similar exceptthat one stores the units decimal digit and the other stores the 10sdigit. As will be understood, additional data is stored in conformancewith the decimal numbering system in additional registers. The BCDrepresentation of the units and 10s is placed in the registers 90 and 91as four bits of information. Each register incorporates output lineswhich are weighted l, 2, 4 and 8. The output conductors from the decimalregisters 90 and 91 are each input to decoding circuits indicated bynumerals 92 and 93. The decoders 92 and 93 convert the four wire, 4-bitrepresentation of the decimal numerals into 10 signals on 10 wires. Ifdesired, a set of power drivers 94 is incorporated in the 10 outputlines. Because of the loading problems, this precuation is best takenwith the apparatus shown. The function of the power drivers is tofurnish a suitable current flow.

The numeral 95 indicates a decade decode .unit which is responsive toinformation in both the registers 90 and 91. The apparatus 95 has tenoutput conductors. Should the X coordinate of the selected terminal bebetween zero and nine, this is represented by some number stored in theregister 90 and a zero stored in the register means 91. The zero fromthe 10sdigit register 91 is symbolized by a signal on the conductor 950which enables all 10 gates within the decade decode unit 95. One form ofthe decade decode unit 95 includes 10 AND gates which are all enabled bythe signal on the conductor 950. Then, one of the plurality ofconductors from the power drivers means 94 conveys a signal whichselects one of the AND gates to form an output signal related to thenumber in the register 90.

Attention is also directed to the decade decode unit 96. It is similarto the decode unit 95, with the exception that a conductor 96a providesa signal from the l0s-digit register 91. The signal results from a onein the tens register and is associated with a number between 10 and 19.The above arrangement is repeated by decades whereby l0 decade decodeunits drive 100 conductors.

Should a greater number of conductors, say 1,000, be desired, thehundreds digit is also stored in a register similar to the registers 90or 91, is converted from BCD to 10 wired signals by means similar to themeans 92 and 93, and additional inputs are provided in each of thedecade decode units to be qualified by the loos-signal level. The aboveprocess is exemplary of one means of decoding the decimalrepresentations of terminals in the matrix 12.

Attention is next directed to FIG. 7 of the drawings which illustrates acoincidence detector means 30 adapted for use in the circuit shown inFIG. 1. For purposes of simplification, the apparatus shown in FIG. 7 isabbreviated because additional digits are handled repetatively. Thenumeral 101 represents a first register for receiving the units decimaldigit in BCD form.

The numeral 102 represents a second and corresponding register, theintention being to compare the decimal numerals stored in the tworegisters. The numerals 103 and 104 each represent the IOs-registorscooperative with the units registers 101 and 102. Each of the decaderegisters is divided into four portions for storing the four bits whichdefine a decimal number. The bits are weighted in some customarypattern, one acceptable pattern being the l, 2, 4, 8 representationadapted for the present invention. Each of the four bits in. theregisters 101 and 102 has output conductors to one of several exclusiveOR gates 106, 107, and so on. An exclusive OR gate is connected toequally weighted bits in the registers for the units, IDs and alladditional decimal numbers without limitation.

The gates 106, 107 and 108, and all similar gates are input to an ORgate 110. The gate 110 provides an output on noncomparison in thefollowing manner. Considering the gate 106 by way of example, should itsinput signals from the registers 102 and 101 be identical, the gate 106provides no output. However, should non-coincidence occur, the gate 106pro vides an output signal to the gate 110. The gate 110 forms an outputsignal which indicates the equality of the numbers stored in theregisters.

The circuitry shown in FIG. 7 is particularly suited for adaption as thecoincidence detectors 30 and 31 shown in FIG. 1.

With a view of fully describing the apparatus incorporated in thepresent invention, it should be noted that the tape reader means 15 andthe digital printer means 43 are normally bought items and many modelsof acceptable equipment are on the market. The various registersincorporated with the present invention are likewise bought items, orelse they can be fabricated. Of course, the registers 20 and 21 storestatic information and are different from the scan registers. Likewise,the registers 28 and 29 do not operate at high speeds. However, the scanregister 24 operates at a high rate of speed because it has the scanclock 36 as the incrementing input. More should be noted concerning thespeed of the registers 24 and 25. The speed of operation of the presentinvention is dependent in large part on the rate of operation of thescan registers 24 and 25. Depending on the character of the circuitryselected, speeds on the order of 100,000 or more hertz are achieved. Thespeed requirements imposed on the scan registers are also imposed on thedecode drivers which select the X and Y" coordinate wires.

Considering further the actual construction of the present invention,the massive OR gate 40 symbolically is shown with inputs from all of theterminals 12. Should there be 10,000 terminals, the gate 40 has 10,000inputs. Since this is unwieldy of fabrication, it is possible to use apyramid of OR gates working up through three or four levels to provide asingle output conductor. For instance, 10,000 terminals can be summed inone OR gate function by 1,111 IO-input OR gates arranged in pyramidfashion; of course, other arrangements are available.

Numerous alterations in the preferred embodiment have been discussedherein and should be considered further. For instance, the matrix 12 isshown as a square pattern. This is not necessarily required. Forinstance, apparatus manufactured for installation in telephone exchangeshas a matrix of 48 by 112 terminals. Assuming the Y" coordinate is thelarger dimension, a third decade is added to the registers storing theY" coordinate data. More specifically, the registers 21, 25 and 29 areincreased to receive a third decimal number. In the above cited example,the 100s digit is de minimus since it can assume only two values, zeroor one, and no other. Therefore, only a l-bit storage means is needed inthis case. Moreover, those skilled in the art can include the gating inthe registers reset to zero on counting to number other than fullcapacity of the register. As discussed hereinbefore, with the 100 by 100pattern, recycling of the X" scan register was accomplished on cyclingthrough 100 steps. This is not required since the appropriate gating isavailable to the art.

Other alterations are within the scope of the present invention, and canbe adapted after achieving an understanding of the disclosure containedherein. However, the scope of the present invention is not limited bythe preferred embodiment described hereinabove, but is within the spiritof the claims appended hereto.

I claim:

1. A test apparatus for testing for undesired electrical connectionsamong a plurality of terminals with selected conductive paths connectedto at least two of such terminals wherein the number of terminals may beincreased essentially without limit and wherein the terminals aresubject to designation in a coordinate system and have locations givenby l, 2, 3, M, and l, 2, 3, 4, N, in X-Y coordinates and the apparatuscomprising:

first means connected to a plurality of the terminals;

said first means including an X storage register means of M capacity anda Y storage register means of N capacity; means for inputting to said Xand Y storage register means a XY designation of a terminal;

signal forming means for imposing an electrical condition at theterminal indicated by the designation in said X and Y storage registermeans; v

a gate means connected to each of the plurality of terminals to bescanned, said gate means being connected to the plurality of terminalsin a manner such that an indicia of the electrical condition of theterminal is communicated to said respective gate means; second X and Ystorage register means having respectively capacities of M and N;

means for inputting a terminal designation signal into said second X andY storage register means of value equal to or less than M and N todesignate a terminal;

connective means connected so said second X and Y storage registermeans, said connective means forming unique enable signals for selectedones of said gate means; said gate means, on receipt of enable signals,enabling said gate means to form output signals related to theelectrical condition of the terminals connected thereto; and,

comparator circuit means provided with output signals from said gatemeans and also adapted to be provided with signals to be compared withsuch output signals, and forming a comparative output signal when thecompared signals achieve a desired comparison.

2. The invention of claim 1 wherein said first means includes switchingtransistor means connected to each of the plurality of terminals, andsaid first X and Y storage register means are connected to saidswitching transistor means such that a unique designation of a terminalencoded as X and Y values equal to or less than M and N respectivelyalters the operative condition of one of said switching transistormeans.

3. The invention of claim 2 wherein said one switching transistor meanshas one terminal connected to one of a plurality of conductors common to'X-coordinates of the terminals, and another terminal connected to oneof a plurality of conductors common to Y-coordinates of the terminals.

4. The invention of claim 3 including a decoder means connected to saidfirst X storage register means which forms a binary signal on only oneof said conductors common to X-coordinate terminals.

5. The invention of claim 3 including a decoder means connected to saidfirst Y storage register means which forms a binary signal on only oneof said conductors common to Y-coordinate terminals.

6. The invention of claim 3 wherein additional of said switchingtransistor means are connected to the one of the plurality of conductorsbut all of which are not altered in operative condition.

7. The invention of claim 6 wherein each of said gate means has threeinputs which are:

the first is connected to the terminal associated therewith;

the second is connected to one of the X-coordinate conductors; and,

the third is connected to one of the Y-coordinate conductOl'S.

8. The invention of claim 1 wherein said comparator means receives as aninput the coordinates in said second X and Y storage register means, andsignals giving X and Y coordinates of a selected terminal.

9. The invention of claim 1 wherein said first X and Y

1. A test apparatus for testing for undesired electrical connectionsamong a plurality of terminals with selected conductive paths connectedto at least two of such terminals wherein the number of terminals may beincreased essentially without limit and wherein the terminals aresubject to designation in a coordinate system and have locations givenby 1, 2, 3, .... M, and 1, 2, 3, 4, .... N, in X-Y coordinates and theapparatus comprising: first means connected to a plurality of theterminals; said first means including an X storage register means of Mcapacity and a Y storage register means of N capacity; means forinputting to said X and Y storage register means a X-Y designation of aterminal; signal forming means for imposing an electrical condition atthe terminal indicated by the designation in said X and Y storageregister means; a gate means connected to each of the plurality ofterminals to be scanned, said gate means being connected to theplurality of terminals in a manner such that an indicia of theelectrical condition of the terminal is communicated to said respectivegate means; second X and Y storage register means having respectivelycapacities of M and N; means for inputting a terminal designation signalinto said second X and Y storage register means of value equal to orless than M and N to designate a terminal; connective means connected sosaid second X and Y storage register means, said connective meansforming unique enable signals for selected ones of said gate means; saidgate means, on receipt of enable signals, enabling said gate means toform output signals related to the electrical condition of the terminalsconnected thereto; and, comparator circuit means provided with outputsignals from said gate means and also adapted to be provided withsignals to be compared with such output signals, and forming acomparative output signal when the compared signals achieve a desiredcomparison.
 2. The invention of claim 1 wherein said first meansincludes switching transistor means connected to each of the pluralityof terminals, and said first X and Y storage register means areconnected to said switching transistor means such that a uniquedesignation of a terminal encoded as X and Y values equal to or lessthan M and N respectively alters the operative condition of one of saidswitching transistor means.
 3. The invention of claim 2 wherein said oneswitching transistor means has one terminal connected to one of aplurality of conductors common to X-coordinates of the terminals, andanother terminal connected to one of a plurality of conductors common toY-coordinates of the terminals.
 4. The invention of claim 3 including adecoder means connected to said first X storage register means whichforms a binary signal on only one of said conductors common toX-coordinate terminals.
 5. The invention of claim 3 including a decodermeans connected to said first Y storage register means which forms abinary signal on only one of said conductors common to Y-Coordinateterminals.
 6. The invention of claim 3 wherein additional of saidswitching transistor means are connected to the one of the plurality ofconductors but all of which are not altered in operative condition. 7.The invention of claim 6 wherein each of said gate means has threeinputs which are: the first is connected to the terminal associatedtherewith; the second is connected to one of the X-coordinateconductors; and, the third is connected to one of the Y-coordinateconductors.
 8. The invention of claim 1 wherein said comparator meansreceives as an input the coordinates in said second X and Y storageregister means, and signals giving X and Y coordinates of a selectedterminal.
 9. The invention of claim 1 wherein said first X and Y storageregister means are incremented by a clock means running freely untilstopped by a predetermined event until said first and second storagemeans have counted jointly to a maximum of M by N in a sequentialpattern.